The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Static random-access memory cells generally consist of two inverters that are coupled to one another through a feedback loop that is stable in only two states and remains in one of these two states as long as the SRAM cell remains connected to a high and low reference potential. In some implementations, the fact that SRAM cells retain a stored state without needing to be refreshed may be an advantage over other types of memory cells, such as dynamic random-access memory (DRAM) cells.
Although SRAM cells retain an information state without requiring to be refreshed, corruption of the stored information state may occur when an SRAM cell is being access for reading or writing. During writing, access transistors that connect the SRAM cell to bitlines may need to be strong enough to “flip” the state of the SRAM cell. In some aspects, this may require the access transistors to be stronger than the transistors that make up the SRAM cells. Although such a design requirement may be incorporated into some implementations, variations of transistor strength during fabrication may render some SRAM cells unusable (e.g., those SRAM cells where the access transistors are too weak due to process variations). Moreover, temperature fluctuations or other spurious effects may prevent SRAM cells in which access transistors are relatively weak from operating reliably.
During read operations, SRAM cells may suffer from read disturbance, for example, when reading takes sufficiently long, such that leakage of the transistors that make up the SRAM cell is large enough to flip the state of the SRAM cell. In this case, the information state stored by and about to be read from the SRAM cell may be compromised, leading to a read error.
In light of the above challenges, there is a need to improve the reliability of reading from and writing to SRAM cells.